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  december 2010 ? 2010 fairchild semiconductor corporation www.fairchildsemi.com FPF1205 / fpf1206 ? rev. 1.0.0 FPF1205 / fpf1206 ? intellimax ? advanced load switch FPF1205 / fpf1206 intellimax ? advanced load switch features ? 1.2v to 4.0v input voltage operating range ? typical r on : 75m ? at v in =3.3v 110m ? at v in =1.8v 240m ? at v in =1.2v ? slew rate control with t r : 110s ? output discharge function on fpf1206 ? low <1.5a quiescent current ? extra low <100na off supply current ? esd protected: above 7000v hbm, 2000v cdm ? gpio/cmos-compatible enable circuitry ? 4-bump wlcsp, 0.76mm x 0.76mm, 0.4mm pitch applications ? mobile devices and smart phones ? portable media devices ? ultra-portable / mobile computing ? advanced notebook, umpc, mid ? portable medical devices ? gps and navigation equipment description the FPF1205/06 is an ultra-small intellimax ? load switch with integrated p-channel switch and analog control features. internal slew-rate control prevents inrush current and the resulting excessive voltage drop on power rail. the input voltage range operates from 1.2v to 4.0v to provide power-disconnect capability for post-regulated power rails in portable and consumer products. the low shut-off current of 1a (maximum) allows power designs to meet standby and off-power drain specifications. the FPF1205/06 is controlled by an active-high logic input (on pin) compatible with standard cmos gpio circuitry found on field programmable gate array (fpga) and embedded processors. the FPF1205/06 is available in a 0.76mm x 0.76mm 4-bump wafer-level chip-scale package (wlcsp). ordering information part number top marking switch (typical) at 3.3v in output discharge on pin activity t r package FPF1205ucx qk 75m ? na active high 110s 4-ball wlcsp, 0.76mm x 0.76mm, 0.4mm pitch fpf1206ucx ql 75m ? 65 ? active high 110s http:///
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FPF1205 / fpf1206 ? rev. 1.0.0 2 FPF1205 / fpf1206 ? intellimax ? advanced load switch application diagram figure 1. typical application notes: 1. c in =1 f, x5r, 0603 (for example, murata grm185r60j105ke26). 2. c out =0.1 f, x5r, 0805 (for example, murata grm216r61a105ka01). functional block diagram v out FPF1205/06 v in on gnd control logic esd protection turn-on slew rate controlled driver output discharge (optional) figure 2. functional block diagram (output discharge for fpf1206 only) http:///
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FPF1205 / fpf1206 ? rev. 1.0.0 3 FPF1205 / fpf1206 ? intellimax ? advanced load switch pin configurations figure 3. wlcsp bumps facing up (top view) figure 4. wlcsp bumps facing down (bottom view) figure 5. pin assignments (top view) figure 6. pin assignments (bottom view) pin definitions pin # name description a1 v out switch output a2 v in supply input, input to the power switch b1 gnd ground b2 on on/off control, active high a 1 a 2 b1 b2 v out on v in gnd a 2 a 1 b2 b1 v in gnd v out on http:///
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FPF1205 / fpf1206 ? rev. 1.0.0 4 FPF1205 / fpf1206 ? intellimax ? advanced load switch absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. unit v in v in , v out , v on to gnd -0.3 4.2 v i sw maximum continuous switch current 1.2 a p d power dissipation at t a =25c 1.0 w t stg storage junction temperature -65 +150 c t a operating temperature range -40 +85 c ja thermal resistance, junction-to-ambient 1s2p with one thermal via 110 c/w 1s2p without thermal via 95 esd electrostatic discharge capability (3,4) human body model, jesd22-a114 7 kv charged device model, jesd22-c101 2 notes: 3. measured using 2s2p jedec std. pcb. 4. measured using 2s2p jedec pcb cold plate method. recommended operating conditions the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter min. max. unit v in supply voltage 1.2 4.0 v t a ambient operating temperature -40 +85 c http:///
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FPF1205 / fpf1206 ? rev. 1.0.0 5 FPF1205 / fpf1206 ? intellimax ? advanced load switch electrical characteristics unless otherwise noted, v in =1.2 to 4.0v and t a =-40 to +85c. typical values are at v in =3.3v and t a =25c. symbol parameter conditions min. typ. max. unit basic operation v in supply voltage 1.2 4.0 v i q(off) off supply current v on =gnd, v out =open, v in =4v 100 na i sd shutdown current v on =gnd, v out =gnd 1 a i q quiescent current i out =0ma 1.5 a r on on resistance v in =3.3v, i out =200ma, t a =25c 75 100 m ? v in =1.8v, i out =200ma, t a =25c 110 150 v in =1.2v, i out =200ma, t a =25c 240 300 v in =1.8v, i out =200ma, t a =85c 160 200 r pd output discharge r pull down v in =3.3v, v on =0v, i force =20ma, t a =25c, fpf1206 65 110 ? v ih on input logic high voltage v in <1.5v 0.9 v v in =1.5v to 4.0v 1.1 v il on input logic low voltage v in =1.2v to 4.0v 0.75 v i on on input leakage v on =v in or gnd 1 a dynamic characteristics (5) t don turn-on delay (6) v in =3.3v, r l =10 ? , c l =0.1f, t a =25c 110 s t r v out rise time (6) 110 t on turn-on time (6) 220 t doff turn-off delay (6) v in =3.3v, r l =10 ? , c l =0.1f, t a =25c, FPF1205 7 s t f v out fall time (6) 2 t off turn-off time (6) 9 t doff turn-off delay v in =3.3v, r l =500 ? , c l =0.1f, t a =25c, FPF1205 10 s t f v out fall time 95 t off turn-off time (6) 105 t doff turn-off delay v in =3.3v, r l =500 ? , c l =0.1f, t a =25c, fpf1206 (7) 7.0 s t f v out fall time 10.5 t off turn-off time (6) 17.5 notes: 5. these parameters are guaranteed by design and characterization; not production tested. 6. t don /t doff /t r /t f are defined in figure 24. 7. output discharge path is enabled during device off. http:///
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FPF1205 / fpf1206 ? rev. 1.0.0 6 FPF1205 / fpf1206 ? intellimax ? advanced load switch typical performance characteristics figure 7. shutdown current vs. temperature figure 8. shutdown current vs. supply voltage figure 9. off supply current vs. temperature (FPF1205, v out floating) figure 10. off supply current vs. supply voltage (FPF1205, v out floating) figure 11. quiescent current vs. temperature figure 12. quiescent current vs. supply voltage 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.90 1.00 -40 -15 10 35 60 85 v in shutdown current ( a) t j , junction temperature (c) on = 0v v in = 4.0v v in = 1.2v v in = 3.3v 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.90 1.00 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v in shutdown current ( a) supply voltage (v) on = 0v 25c 85c -40c 0.00 0.05 0.10 0.15 0.20 0.25 0.30 -40 -15 10 35 60 85 off supply current ( a) t j , junction temperature (c) on = 0v v in = 4.0v v in = 1.2v v in = 3.3v 0.00 0.05 0.10 0.15 0.20 0.25 0.30 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 off supply current ( a) supply voltage (v) on = 0v 25c 85c -40c 0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 -40 -15 10 35 60 85 supply current ( a) t j , junction temperature (c) on = v in v in = 4.0v v in = 1.2v v in = 3.3v 0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 1.80 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 supply current ( a) supply voltage (v) 25c 85c -40c on = v in http:///
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FPF1205 / fpf1206 ? rev. 1.0.0 7 FPF1205 / fpf1206 ? intellimax ? advanced load switch typical performance characteristics figure 13. r on vs. temperature figure 14. r on vs. supply voltage figure 15. on-pin threshold vs. v in figure 16. load current vs. v in - v out figure 17. v out rise and fall time vs. temperature at r l =10 figure 18. v out turn-on and turn-off delay vs. temperature at r l =10 ? 0 20 40 60 80 100 120 140 160 -40 -15 10 35 60 85 on resistance (m ) t j , junction temperature (c) on = v in i out = 200ma v in = 4.0v v in = 1.2v v in = 3.3v 0 20 40 60 80 100 120 140 160 1.2 1.7 2.2 2.7 3.2 3.7 4.2 4.7 5.2 on resistance (m ) supply voltage (v) 25c 85c -40c on = v in i out = 200ma 0.70 0.75 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 1.01.52.02.53.03.54.0 on input logic voltage (v) supply voltage (v) 25c v ih v il 1 10 100 1000 -40 -15 10 35 60 85 rise/fall time (us) t j , junction temperature (c) t r t f v in = 3.3v c l = 0.1f r l = 10 0 10 20 30 40 50 60 70 80 90 100 -40 -15 10 35 60 85 on/off delay time (s) t j , junction temperature (c) t doff t don v in = 3.3v c l = 0.1f r l = 10 http:///
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FPF1205 / fpf1206 ? rev. 1.0.0 8 FPF1205 / fpf1206 ? intellimax ? advanced load switch typical performance characteristics figure 19. v out rise and fall time vs. temperature at r l =500 figure 20. v out turn-on and turn-off dela y vs. temperature at r l =500 figure 21. turn-on response (v in =3.3v, c in =1f, c out =0.1f, r l =10 ? ) figure 22. turn-off response (v in =3.3v, c in =1f, c out =0.1f, r l =10 ? ) figure 23. turn-off response (FPF1205 = no output pull-down resistor) (v in =3.3v, c in =1f, c out =0.1f, r l =500 ? ) figure 24. timing diagram notes: 8. t on =t r + t don . 9. t off =t f + t doff . 50 55 60 65 70 75 80 85 90 95 100 -40 -15 10 35 60 85 rise/fall time ( s) t j , junction temperature (c) t r v in = 3.3v c l = 0.1 f r l = 500 t f 0 10 20 30 40 50 60 70 80 90 -40 -15 10 35 60 85 on/off delay time (s) t j , junction temperature (c) t doff t don v in = 3.3v c l = 0.1f r l = 500 10% v on v out v out t don t doff 10% 3.3v 90% t f 90% t r 90% 10% 50% 50% http:///
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FPF1205 / fpf1206 ? rev. 1.0.0 9 FPF1205 / fpf1206 ? intellimax ? advanced load switch operation and application description the FPF1205 and fpf1206 are low-r on p-channel load switches with controlled turn-on. the core of each device is a 50m p-channel mosfet and controller capable of functioning over a wide input operating range of 1.2 - 4.0v. the on pin, an active high giop / cmos-compatible input, controls the state of the switch. the fpf1206 contains a 65 on-chip load resistor for quick output discharge when the switch is turned off. input capacitor to limit the voltage drop on the input supply caused by transient inrush current when the switch turns on into a discharged load capacitor or short-circuit, a capacitor must be placed between the v in and gnd pins. a 1f ceramic capacitor, c in , placed close to the pins is usually sufficient. higher-value c in can be used to reduce the voltage drop in higher-current applications. output capacitor a 0.1f capacitor, c out , should be placed between the v out and gnd pins. this capacitor prevents parasitic board inductance from forcing v out below gnd when the switch is on. c in greater than c out is highly recommended. c out greater than c in can cause v out to exceed v in when the system supply is removed. this could result in current flow through the body diode from v out to v in . board layout for best performance, all traces should be as short as possible. to be most effective, the input and output capacitors should be placed close to the device to minimize the effect that parasitic trace inductance may have on normal and short-circuit operation. using wide traces or large copper planes for all pins (v in , v out , on, and gnd) helps minimize the parasitic electrical effects along with minimizing the case ambient thermal impedance. however, the v out pin of fpf1206 should not connect directly the battery source due to the discharge mechanism of the load switch. figure 25. typical application http:///
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FPF1205 / fpf1206 ? rev. 1.0.0 10 FPF1205 / fpf1206 ? intellimax ? advanced load switch physical dimensions figure 26. 4 ball, 0.76 x 0.76 mm wafer-level chip-scale wlcsp packaging product-specific dimensions product d e x y FPF1205ucx 760m 30m 760m 30m 0.180mm 0.018m 0.180mm 0.018m fpf1206ucx 760m 30m 760um 30m 0.180mm 0.018m 0.180mm 0.018m package drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packaging are a for the most recent package drawing: http://www.fairchildsemi.com/packaging/. bottom view side views top view recommended land pattern ball a1 index area a1 0.005 cab f (nsmd pad type) b a 0.2920.018 0.2080.021 notes: a. no jedec registration applies. b. dimensions are in millimeters. c. dimensions and tolerance per asme y14.5m, 1994. d. datum c is defined by the spherical crowns of the balls. e. package nominal height is 500 microns 39 microns (461-539 microns). f. for dimensions d, e, x, and y see product datasheet. g. drawing filname: mkt-uc004afrev1. 0.03 c 2x 0.03 c 2x 12 a b 0.40 0.40 (x)0.018 seating plane c 0.06 c 0.05 c e d d e 0.40 0.40 ?0.20 cu pad ?0.30 solder mask (y)0.018 ?0.2600.020 4x 0.539 0.461 f http:///
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FPF1205 / fpf1206 ? rev. 1.0.0 11 FPF1205 / fpf1206 ? intellimax ? advanced load switch http:///


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